The present invention relates to a high power switching semiconductor device which has high input impedance and high speed switching characteristics.
It is known in the art to employ a bipolar transistor or an insulated gate transistor as power switching semiconductor devices. A typical bipolar transistor construction is shown in FIG. 1 wherein reference numeral 1 denotes a base electrode, numeral 2 a base region (P), numeral 3 an emitter electrode, numeral 4 an emitter region (N), numeral 5 a collector region (N.sup.-), numeral 6 a collector region (N.sup.+) having a higher impurity concentration than the collector region 5, and numeral 7 a collector electrode. This bipolar transistor is of the current control type, in which a minority carrier injection from the emitter region 4 is excited by a base current to collect most of the minority carriers in the collector through the base region 2. The low input impedance bipolar transistor of this type cannot, however, effectively respond to use in high speed switching operations, and its operating range is further restricted due to secondary breakdown.
FIG. 2 shows a conventional insulated gate transistor wherein reference numeral 8 denotes a gate electrode, numeral 9 a gate oxide film, numeral 10 a source electrode, numeral 11 a source region (N.sup.+), numeral 12 a channel region (P), numeral 13 a drain region (N.sup.-) having a low impurity concentration, numeral 14 a drain region (N.sup.+) having a high impurity concentration, and numeral 15 a drain electrode. This insulated gate transistor is a voltage drive type switching element and is typically utilized as a power switching element because of its high input impedance and high speed switching characteristics. However, it is difficult to form the insulated gate transistor with a low resistance region and its unipolar type construction is not well suited for high power applications because, in use, majority carriers flow between the source and the drain due to channel induction.
FIG. 3 shows the structure of an insulated gate transistor of the conductivity modulated type, which are considered to be an improvement over the devices described above. In FIG. 3, the common portions shared with FIG. 2 are denoted with identical reference numerals. The structure of FIG. 3 is different from that of FIG. 2 in that a drain region 16 (P.sup.+) having a conductivity type opposed to that of the drain region 14 of FIG. 2 is formed to effect injection of the minority carriers from the drain region. A conductivity modulation is effected in the drain region 13 (N.sup.-) so as to enlarge the current density, thereby giving the device of FIG. 3 lower resistance and a higher operating power range. This device is susceptible to exhibiting an unwanted thyristor operation, because of the N-P-N-P structure, and is intended to suppress occurrence of latchup phenomena. FIG. 4 shows an improvement over the structure of FIG. 3. In FIG. 4, the common portions shared with FIG. 3 are denoted with identical reference numerals. The improvement resides in a low resistance layer 17 (P.sup.+), of the same conductivity type as the channel region 12, formed below the channel region 12 to dampen, as much as possible, the injection of minority carriers into the source region 11 (N.sup.+) channel. This reduces the voltage drop between the source and the drain due to hole current to prevent occurrence of latchup. Although the description of the devices herein is directed to the case of an N-channel element, the conductivity types N and P may be wholly inverted for a P-channel element.
These known devices suffer a great deficiency in that during the fabrication thereof, if the low resistance layer 17 is to be formed below or in the channel region 12, as shown in FIG. 4, it is difficult to cause the low resistance layer 17 to completely enclose the channel region, excluding the current path of the majority carriers from the source region 11 to the drain region 13, without eliminating the channel portion. Since, moreover, it is impossible to reduce the resistance of the low resistance layer 17 infinitely without influencing the channel portion, the reduction in the voltage drop due to the minority carriers between the source and the drain is restricted. The fabrication of this conductivity modulated type transistor results in a structure which does not eliminate the channel portion of the channel forming region, which is necessary to dampen the injection of minority carriers into the source region to thereby reduce the voltage drop caused by the minority carrier current, since the current path of the majority carriers from the source region to drain region is enclosed completely within the low resistance layer. Furthermore, it is extremely difficult to control the channel length partly because the formation of the channel region 12 and the source region 11 are performed by a double diffusion process using the gate electrode 8 as a diffusion mask, and partly because restrictions are imposed upon the impurity of materials and the diffusion conditions used to form those regions.
Therefore, it is an object of the present invention to provide a novel insulated gate field effect transistor having a high input impedance and high speed switching characteristics, and which has a structure that will cause conductivity modulation for low current density. It is a further object of the invention to provide a novel insulated gate field effect transistor which has high input impedance and is useful for high power application, and can be fabricated without any of the aforementioned deficiencies of the prior art devices. It is a still further object of the invention to prevent occurrences of thyristor operation and latchup associated with insulated gate transistors of the conductivity modulated type.